3.3 volt zero delay, low skew buffer ics2305 mds 2305 d 1 revision 022505 integrated circuit systems 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com 3.3 v olt z ero d elay , l ow s kew b uffer description the ics2305 is a low phase noise, high-speed pll based, low-skew zero delay buffer. based on ics? proprietary low jitter phase locked loop (pll) techniques, the device provides four low skew outputs at speeds up to 133 mhz at 3.3 v. the outputs can be generated from the pll (for zero delay), or directly from the input (for testing), and can be set to tri-state mode or to stop at a low level. the pll feedback is on-chip and is obtained from the clkout pad. the ics2305 is available in two different versions. the ics2305-1 is the base part. the ics2305-1h is a high drive version with faster rise and fall times. features ? clock outputs from 10 to 133 mhz ? zero input-output delay ? four low skew (<250 ps) outputs ? device-to-device skew <700 ps ? full cmos outputs with 25 ma output drive capability at ttl levels ? 5 v tolerant clkin ? tri-state mode for board-level testing ? advanced, low power, sub-micron cmos process ? operating voltage of 3.3 v ? industrial temperature range available ? packaged in 8-pin soic ? available in pb (lead ) free package block diagram clk4 clk3 clk2 clk1 clkin pll vdd gnd clkout idt? / ics? 3.3 volt zero delay, low skew buffer ics2305 1 data sheet ics2305
idt? / ics? 3.3 volt zero delay, low skew buffer ics2305 2 ics2305 3.3 volt zero delay, low skew buffer tsd 3.3 v olt z ero d elay , l ow s kew b uffer mds 2305 d 2 revision 022505 integrated circuit systems 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics2305 pin assignment pin descriptions 1 2 clkin clkout 3 clk2 4 clk1 clk4 gnd vdd clk3 8 7 6 5 8pin ( 150 mil ) soic pin number pin name pin type pin description 1 clkin input clock input (5 v tolerant). 2 clk2 output buffered clock output 2. 3 clk1 power buffered clock output 1 4 gnd power connect to ground. 5 clk3 output buffered clock output 3 6 vdd power power supply. connect to 3.3 v. 7 clk4 output buffered clock output 4. 8 clkout output buffered output. internall feedback on this pin.
idt? / ics? 3.3 volt zero delay, low skew buffer ics2305 3 ics2305 3.3 volt zero delay, low skew buffer tsd 3.3 v olt z ero d elay , l ow s kew b uffer mds 2305 d 3 revision 022505 integrated circuit systems 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics2305 external components the ics2305 requires a minimum number of external components for proper operation. decoupling capacitors of 0.01 mf should be connected betwe en vdd and gnd on pins 4 and 5, and vdd and gnd on pins 13 and 12, as close to the device as possible. a series termination resistor of 33 ? may be used to each clock output pin to reduce reflections. absolute maximum ratings stresses above the ratings listed below can cause per manent damage to the ics2305. these ratings, which are standard values for ics commercially rated part s, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods can affect product reliability. electr ical parameters are guaranteed on ly over the recommended operating temperature range. recommended operation conditions item rating supply voltage, vdd 7 v all inputs and outputs -0.5 v to vdd+0.5 v clkin and fbin inputs -0.5 v to 5.5 v electrostatic discharge (hbm) 2000 v ambient operating temperature (commercial) 0 to +70 c ambient operating temperature (industrial) -40 to +85 c storage temperature -65 to +150 c junction temperature 150 c soldering temperature 260 c parameter min. typ. max. units ambient operating temperature (industrial) -40 +85 c ambient operating temperature (commercial) 0 +70 c power supply voltage (measured in respect to gnd) +3.0 +3.6 v
idt? / ics? 3.3 volt zero delay, low skew buffer ics2305 4 ics2305 3.3 volt zero delay, low skew buffer tsd 3.3 v olt z ero d elay , l ow s kew b uffer mds 2305 d 4 revision 022505 integrated circuit systems 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics2305 dc electrical characteristics ics2305m-xx , vdd = 3.3 v 10%, ambient temperature -40 to +85 c(industrial), (0-70 c commercial) note 1: when there is no clock signal present at clkin, the ics2305 will en ter power down mode. the pll is stopped and the outputs are tri-state. ac electrical characteristics ics2305m-1 , vdd=3.3 v 10%, ambient temperature -40 to +85 c(industrial), (0-70 c commercial) note 2: with vdd at a steady rate and valid input at clkin. parameter symbol conditions min. typ. max. units operating voltage vdd 3.0 3.6 v input high voltage v ih 2v input low voltage v il 0.8 v input low current i il vin = 0v 50 a input high current i ih vin = vdd 100 a output high voltage v oh i oh = -12 ma 2.4 v output low voltage v ol i ol = 12 ma 0.4 v operating supply current idd no load 32 ma power down supply current clkin = 0, note 1 12 a short circuit current i os each output 50 ma input capacitance c in clkin 5 pf parameter symbol conditions min. typ. max. units output clock frequency f in 10 pf load 10 133 mhz output clock frequency 30 pf load 10 100 mhz output rise time t or 0.8 to 2.0 v, outputs loaded 2.5 ns output fall time t of 2.0 to 0.8 v, outputs loaded 2.5 ns output clock duty cycle t dc measured at 1.4v, fout=66.67 mhz 40 50 60 % output clock duty cycle t dc measured at 1.4v, fout=50 mhz 45 50 55 % device to device skew rising edges at vdd/2 700 ps output to output skew rising edges at vdd/2 250 ps input to output skew rising edges at vdd/2 350 ps cycle to cycle jitter measured at 66.67m, outputs loaded 200 ps pll lock time note 2 1.0 ms
3.3 v olt z ero d elay , l ow s kew b uffer mds 2305 d 5 revision 022505 integrated circuit systems 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics2305 ICS2305M-1H , vdd=3.3 v 10%, ambient temperature -40 to +85 c(industrial), (0-70 c commercial), note 3: with vdd at a steady rate and valid input at clkin thermal characteristics parameter symbol conditions min. typ. max. units output clock frequency f in 10 pf load 10 133 mhz output clock frequency 30 pf load 10 100 mhz output rise time t or 0.8 to 2.0 v, outputs loaded 1.5 ns output fall time t of 2.0 to 0.8 v, outputs loaded 1.5 ns output clock duty cycle t dc measured at 1.4v, fout=66.67 mhz 40 50 60 % output clock duty cycle t dc measured at 1.4v, fout=50 mhz 45 50 55 % device to device skew rising edges at vdd/2 700 ps output to output skew rising edges at vdd/2 250 ps input to output skew rising edges at vdd/2 350 ps cycle to cycle jitter measured at 66.67m, outputs loaded 200 ps pll lock time note 3 1.0 ms parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 120 c/w ja 1 m/s air flow 115 c/w ja 3 m/s air flow 105 c/w thermal resistance junction to case jc 58 c/w idt? / ics? 3.3 volt zero delay, low skew buffer ics2305 5 ics2305 3.3 volt zero delay, low skew buffer tsd
idt? / ics? 3.3 volt zero delay, low skew buffer ics2305 6 ics2305 3.3 volt zero delay, low skew buffer tsd 3.3 v olt z ero d elay , l ow s kew b uffer mds 2305 d 6 revision 022505 integrated circuit systems 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics2305 package outline and package dimensions (8-pin soic, 150 mil. narrow body) package dimensions are kept current with jedec publication no. 95 index area 1 2 8 d e seating plane a1 a e - c - b .10 (.004) c c l h h x 45 millimeters inches symbol min max min max a 1.35 1.75 .0532 .0688 a1 0.10 0.25 .0040 .0098 b 0.33 0.51 .013 .020 c 0.19 0.25 .0075 .0098 d 4.80 5.00 .1890 .1968 e 3.80 4.00 .1497 .1574 e 1.27 basic 0.050 basic h 5.80 6.20 .2284 .2440 h 0.25 0.50 .010 .020 l 0.40 1.27 .016 .050 0 8 0 8
ics2305 3.3 volt zero delay, low skew buffer tsd 3.3 v olt z ero d elay , l ow s kew b uffer mds 2305 d 7 revision 022505 integrated circuit systems 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics2305 ordering information ?lf? denotes pb (lead free) package. while the information presented herein has been checked for both ac curacy and reliability, integrated circuit systems (ics) ass umes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result f rom its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other appli cations such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recomme nded without additional processing by ics. ics reserves the right to change any circui try or specifications without notice. ics does not aut horize or warrant any ics product for use in life support de vices or critical medical instruments. part / order number marking shipping packaging package temperature ics2305mi-1 2305mi-1 tubes 8-pin soic -40 to +85 c ics2305mi-1t 2305mi-1 tape and reel 8-pin soic -40 to +85 c ics2305mi-1h 2305mi1h tubes 8-pin soic -40 to +85 c ics2305mi-1ht 2305mi1h tape and reel 8-pin soic -40 to +85 c ics2305mi-1lf 2305mi1l tubes 8-pin soic -40 to +85 c ics2305mi-1lft 2305mi1l tape and reel 8-pin soic -40 to +85 c ics2305mi-1hlf 2305i1hl tubes 8-pin soic -40 to +85 c ics2305mi-1hlft 2305i1hl tape and reel 8-pin soic -40 to +85 c ics2305m-1 2305m-1 tubes 8-pin soic 0 to +70 c ics2305m-1t 2305m-1 tape and reel 8-pin soic 0 to +70 c ICS2305M-1H 2305m-1h tubes 8-pin soic 0 to +70 c ICS2305M-1Ht 2305m-1h tape and reel 8-pin soic 0 to +70 c ics2305m-1lf 2305m1lf tubes 8-pin soic 0 to +70 c ics2305m-1lft 2305m1lf tape and reel 8-pin soic 0 to +70 c ICS2305M-1Hlf 2305m1hl tubes 8-pin soic 0 to +70 c ICS2305M-1Hlft 2305m1hl tape and reel 8-pin soic 0 to +70 c idt? / ics? 3.3 volt zero delay, low skew buffer ics2305 7
idt? / ics? 3.3 volt zero delay, low skew buffer ics2305 8 ics2305 3.3 volt zero delay, low skew buffer tsd 3.3 v olt z ero d elay , l ow s kew b uffer mds 2305 d 8 revision 022505 integrated circuit systems 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics2305 revision history rev. originator date description of change a p. griffith 12/01/04 new device/datasheet; preliminary. b p. griffith 12/27/04 made corrections to idd, iddp, input capacitance, duty cycle and jitter specs/test conditions. removed reference to table 2 in output clock frequency test conditions. removed abslolute and cycle-to-cycle jitter specs for 15 pf load. added duty cycle spec for fout=50 mhz. release from preliminary to final. c p. griffith 1/25/05 made corrections to test conditions of output rise time, fall-time, duty cycle and cycle-to-cycle jitter. d j. sarma 2/25/05 added lf packing info.
ics2305 3.3 volt zero delay, low skew buffer tsd ics1890 auto-negotiation advertisement register (register 4 [0x04]) tsd mk1491-14 opti acpi firestar clock source tsd ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa xx-xxxx-xxxxx corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support clockhelp@idt.com 408-284-8200 innovate with idt and accelerate your future networks. contact: www.idt.com ics280 triple pll field prog. spread spectrum clock synthesizer tsd
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